Conventionally, there has been a subsystem including multiple memory circuits and an interface circuit capable of communicating with a system, in which the interface circuit provides an interface between the memory circuits and the system, and operates so that restrictions on the memory circuits for instruction scheduling are reduced. In such a subsystem, a circuit may be added, which controls a slew rate, pull-up capability or strength, and pull-down capability or strength for each pin in addition to timing calibration capability and compensation capability, to each I/O pin of an integrated buffer circuit, or added as a common circuit for a suite of I/O pins of the integrated buffer circuit.
Also, there is a semiconductor device characterized by a memory part for storing characteristic information that indicates intrinsic electrical characteristics of the semiconductor device, which makes it possible to adjust buffering capability of the semiconductor device based on the stored characteristic information in the memory part. As such characteristic information, characteristic variation information, slew rate, driving capability, voltage amplitude, current characteristic, and the like of the semiconductor device measured beforehand are stored in the memory part.